git.cappig.dev / apheleiaOS.git master

ab1607d0259ba2602440e88578e0849f2455486b master
cappig <[email protected]> ยท 4 months ago
Symbol loading from ELF, AHCI/ATA PCI probing, PTY VMIN/VTIME

* Replace nm sym.map symbol loader with direct ELF section parsing;
  load_symbols() reads .symtab/.dynsym from the kernel ELF on disk,
  drop libs/parse/sym.c and the nm/SYMBOL_MAP build targets
* Overhaul AHCI controller discovery: scan SATA/RAID/ATA PCI
  subclasses, decode 64-bit BARs, accept sig==0 ports, add fallback
  port selection, validate HBA cap before use
* Add PCI IDE probing to ATA: read BAR0-3 for native-mode channels,
  enable bus mastering; ata_probe_channel gains use_irq parameter;
  fall back to legacy IO ports if no PCI IDE found
* Implement _queue_read_termios() in pty.c with POSIX VMIN/VTIME
  raw-mode semantics; slave reads use it instead of plain _queue_read
* Add vi frame cache: build each row into a fixed buffer and only emit
  escape sequences for rows that changed; EINTR loop fix in read_key
13 files changed, 763 insertions, 330 deletions
kernel/arch/x86/ahci.c +91 -50
kernel/arch/x86/ata.c +103 -6
kernel/arch/x86/build/build.mk +5 -15
kernel/main.c +4 -3
kernel/sys/pty.c +131 -2
kernel/sys/symbols.c +218 -43
kernel/sys/symbols.h +10 -1
kernel/sys/vfs.c +1 -6
libs/parse/sym.c removed
libs/parse/sym.h removed
makefile +1 -1
user/vi/main.c +191 -83
utils/toolchain.mk +8 -15